The present invention relates to read and write schemes for use in items such as Static Random Access Memory (SRAM) arrays and register files.
Power consumption in highly integrated silicon chips has become increasingly important. Memory elements are a significant contributor to power consumption due to their size and the area that they occupy. The present invention proposes a new read and write scheme that lowers read power significantly in single-ended memory type read schemes, which are used in items such as SRAM arrays and register files.
A typical static memory cell, a SRAM cell 01, is shown in FIG. 1 and consists of a cross-coupled inverter pair 02 and two read/write- or pass-devices 03 (hereinafter “pass-devices”), one on each side. The cell 01 is differentially written through the two pass-devices 03 by applying a differential signal at two bitlines true (blt) 04 and complement (blc) 05. For example, when writing a ‘1’, blt 04 is high while blc 05 is low. This guarantees a robust functionality across a wide process window and mismatches between the devices 03, 06 within the same cell 01. Both pass-devices 03 are connected to the same wordline 07 signal wl, which selects the cell 01 for writing.
For read, two schemes have been established: Differential sense-amp read schemes and single-ended read schemes (e.g., single-ended ripple-domino read schemes).
Differential sense-amp read schemes precharge both bitlines 04, 05 to the same high logic voltage Vdd and select the cell 01 through the same wordline 07. Then, the cell 01 discharges one of the two bitlines 04 and 05 depending on its content while keeping the other side high. Subsequently, a sense-amp circuit detects the voltage difference between the two signals (i.e., bitlines 04, 05) and latches its value. These schemes rely on a differential bitline signal for read and/or write.
From Ryuhei Sasagawa et al. ‘High-speed Cascode Sensing Scheme for 1.0 V Contact Programming Mask Rom’, 1999 Symposium on VLSI Circuits, Digest of Technical Papers, pps 95-96, and from Kenichi Imamiya et al, ‘A 68-ns 4-Mbit CMOS EPROM with High-Noise-Immunity Design’, 1990, IEEE Journal of Solid State Circuits Vol. 25, Issue 1, pps. 72-78, single-ended read schemes are known.
In a single-ended read scheme, such as a single-ended ripple-domino read scheme, only one of the two bitlines 04, 05 is actually used for the read. After the cell 01 is selected by the wordline 07, the cell 01 either holds or discharges the bitlines 04, 05. A receiver circuit is switched after the bitline level drops below a certain level. The advantage of this scheme is that it is more robust against process variations seen in current and future technologies such as 90 nm and beyond.
From a power perspective, in read mode both of the bitlines 04, 05 are always precharged to a high voltage level before the cell 01 is selected. Then, one of the two bitlines 04, 05 is pulled down. The power consumption is always the same, regardless of whether the cell 01 holds a ‘one’ or a ‘zero’ and even if only one side is used for read.